1. Field of the Invention
The present invention relates to a semiconductor memory device such as a non-volatile memory (e.g., an EPROM) which allows electrical write.
2. Description of the Related Art
FIG. 16 is a diagram schematically showing the construction of a conventional EPROM. See Japanese Patent Kokai (Laid-Open) Publication No. 2000-331486, for example. Further, FIG. 17 is a diagram schematically showing the construction of four memory cells in the EPROM of FIG. 16. Furthermore, FIGS. 18 and 19 are diagrams for describing the problems in the EPROM of FIG. 16.
The EPROM shown in FIG. 16 has memory arrays 100, . . . , 10n provided with plural memory cells 11 (in distinguishing and describing each, the symbols 11a, 11b, 11c and 11d are also used) formed in a semiconductor substrate. In the semiconductor substrate in which the memory arrays 100, . . . , 10n on are formed, plural word lines WL0, . . . , WLn are arranged mutually in parallel, plural drain lines DL0, . . . , DLy, DLz are arranged intersecting perpendicularly with the word lines WL0, . . . , WLn, and plural source lines SL0, . . . , SLy, SLz are arranged intersecting perpendicularly with the word lines WL0, . . . , WLn. As shown in FIG. 17, the memory cell 11 (11a, 11b, 11c and 11d) includes, for example, field effect transistors which have gates GA, drains DRa, DRbc and DRd, sources SOUab and SOUcd, and floating gates FGa, FGb, FGc and FGd. The gates of the plural memory cells 11 are connected to one of the plural word lines WL0, . . . , WLn. Each drain of the plural memory cells 11 is connected to one of the plural drain lines DL0, . . . , DLz, and each source of the plural memory cells 11 is connected to one of the plural source lines SL0, . . . , SLz. In addition, the actual EPROM has circuits such as an address decoder for generating decoded signals DEC0, . . . , DECn, and a sense amplifier to read the data stored in the memory cell, these not being shown in the figures.
In each of the memory arrays 100, . . . , 10n, the drain lines DL0, . . . , DLy, DLz are respectively connected via NMOS transistors 120, . . . , 12y1 (or 12y2), 12z1 (or 12z2) to a write control line 13, to which a drain drive voltage (write control signal) MCD is supplied. In each of the memory arrays 100, . . . , 10n, ON/OFF control of the even-numbered NMOS transistors 120, 122, . . . , 12y1, 12z1 is performed by even number selection signals SE0, . . . , SEn, respectively, and ON/OFF control of the odd-numbered NMOS transistors 121, 123, . . . , 12y2, 12z2 is performed by odd number selection signals SO0, . . . , SOn, respectively. Moreover, in each of the memory arrays 100, . . . , 10n, the source lines SL0, . . . , SLy, SLz are connected to the bit lines BL0, . . . , BLy, BLz via the NMOS transistors 140, . . . , 14y, 14z which are ON/OFF controlled by memory array selection signals SS0, . . . , SSn.
The EPROM shown in FIG. 16 includes word line drive circuits 200, . . . , 20n which supply drive signals to each of the word lines WL0, . . . , WLn, a write control circuit 30 which supplies the drain drive voltage MCD to the write control line 13, data write circuits 401 and 402 which supply data BLA1 and BLA2 (data supplied to the bit lines BLy and BLz are represented as BLA3 and BLA4, respectively) to the bit lines BL0, . . . , BLy, BLz (the data write circuits 403 and 404 supply data BLA3 and BLA4 to the bit lines BLy and BLz, respectively), and a delay circuit 50 which delays a reset signal RST and outputs the delayed reset signal as a reset signal RST1. The input of the data write circuits 403 and 404 is a power supply voltage VCC which is at high level (H-level).
The word line drive circuits 200, . . . , 20n have mutually identical constructions. The word line drive circuits 200, . . . , 20n respectively generate and output word line selection signals (word line drive voltages) to be supplied to the word lines WL0, . . . , WLn in accordance with the decoded signals DEC0, . . . , DECn supplied from the address decoder. When the decoded signals DEC0, . . . , DECn are at low level (L-level) which represents “non-selection”, the word line drive circuits 200, . . . , 20n output a ground voltage GND to the word lines WL0, . . . , WLn as a word line selection signal. When the decoded signals DEC0, . . . , DECn are at H-level which represents “selection”, the word line drive circuits 200, . . . , 20n function according to a program mode signal “˜PGM” (in this specification, “˜PGM” means “PGM” with an upper line (i.e., overline), and represents the inverse signal of the signal PGM. In the figures, “˜PGM” is represented as “PGM” with an upper line. During data write, the word line drive circuits 200, . . . , 20n output a program voltage VPP (e.g., 10 V) to the word lines WL0, . . . , WLn as a word line selection signal, and during data read, output the power supply voltage VCC to the word lines WL0, . . . , WLn as a word line selection signal.
During data write, the reset signal RST inputted to the write control circuit 30 is at L-level, the drain drive voltage MCD outputted from the write control circuit 30 is determined by the program voltage VPP and the control voltage VR, and is a voltage VCC+2Vtn (where Vtn is a threshold voltage of the NMOS transistor, and is approximately 1 V). The reset signal RST is at H-level during data read. At this time, the drain drive voltage MCD outputted from the write control circuit 30 is the ground voltage GND.
The data write circuits 401, 402, 403 and 404 have mutually identical constructions. When the program mode signal ˜PGM is caused to be L-level to perform a data write operation, the data write circuits 401 and 402 output the ground voltage GND or the write signals BLA1 and BLA2 of the power supply voltage VCC from a node N40 according to the L-level or H-level of input data D1 and D2. The data write circuits 401, 402, 403 and 404 are configured in such a way that when a data read operation is performed by the program mode signal ˜PGM, the node N40 of the data write circuits 401 and 402 is in a high impedance state.
For example, the data write circuit 401 includes an inverter 41 to which the input data D1 is supplied, a NOR gate 42 which outputs the negative logical sum of the output signal of the inverter 41 and the program mode signal ˜PGM, and a NOR gate 43 which outputs the negative logical sum of the output signal of the NOR gate 42 and the program mode signal ˜PGM. The data write circuit 401 also includes an NMOS transistor 44 which is connected between the node N40 and the ground voltage GND, and is controlled by the output signal of the NOR gate 43, an NMOS transistor 45 which is connected between the power supply voltage VCC and the node N40, and is controlled by the output signal of the NOR gate 42, and an NMOS transistor 46 which is connected between the node N40 and the ground voltage GND, and is controlled by the reset signal RST1 outputted from the delay circuit 50.
The write signals BLA1 and BLA2 outputted from the data write circuit 401 and 402 are respectively supplied, for example, to the adjacent bit lines BL0 and BL1 via the transistors 60a and 60b selected by column selection signals Y0 and Y1.
When a logical value low (represented by ‘L’) is written as data into the memory cell 11 selected by the word line WLi (a subscript “i” is an integer from 0 to n) even number selection signal SEj or the odd number selection signal SOj (a subscript “j” is an integer from 0 to n), memory array selection signal SSj, and column selection signal Yk (a subscript “k” is an integer greater than 0), the data D1 inputted to the data write circuit 40, is at L-level. At this time, the gate voltage Vg of the memory cell 11 is 10 V, the drain voltage Vd is VCC+2Vtn (=6 V), and the source voltage Vs is 0 V. Therefore, in the memory cell 11, a large current Ia1 flows from the drain to the source (e.g., in FIG. 17, from the drain DRa to the source SOUab), and due to the avalanche hot carrier generated by this current, electrons are injected into the floating gate (e.g., in FIG. 17, the floating gate FGa).
On the other hand, when a high logical value (represented by ‘H’) is written as data into the memory cell 11 selected by the word line WLj, even number selection signal SEj or odd number selection signal SOj, memory array selection signal SSj and column selection signal Yk, the input data D2 is at H-level. At this time, the gate voltage Vg of the memory cell 11 is 10 V and the drain voltage Vd is VCC−2Vtn (=3 V). Therefore, in the memory cell 11, only a relatively small current Id1 flows from the drain to the source (e.g., in FIG. 17, from the drain DRd to the source SOUcd), and electrons are not injected into the floating gate (e.g., in FIG. 17, the floating gate FGd) because no avalanche hot carriers are generated.
In the aforesaid conventional EPROM, two adjacent bit lines BLk and BLk+1 are selected simultaneously by the column selection signal Yk. The data (e.g., data BLA1 and BLA2) outputted from the data write circuits (e.g., data write circuits 401 and 402) are written respectively into two memory cells 11 connected to the selected bit lines BLk and BLk+1. In FIG. 16, the data BLA1 and BLA2 are written simultaneously into the memory cells 11a and 11d selected by the word line WL0, even number selection signal SE0, memory array selection signal SS0, and the column selection signal Y0, respectively. For example, if the memory cell 100 is selected by the memory array selection signal SS0, the word line WL0 is selected by the word line drive circuit 20n, the bit lines BL0 and BL1 are selected by the column selection signal Y0, and the drain lines DL0 and DL2 are selected by the even number selection signal SE0, current flows from the drain line DL0 via the memory cell 11a, source line SL0, NMOS transistor 140, and bit line BL0. As a result, a charge accumulates in the floating gate of the memory cell 11a (when it has the logical value ‘L’), or does not accumulate in it (when it has the logical value ‘H’). Also, current flows from the drain line DL2 via the memory cell 11d, source line SL1, NMOS transistor 141, and bit line BL1. As a result, a charge accumulates in the floating gate of the memory cell 11d (when it has the logical value ‘L’), or does not accumulate in it (when it has the logical value ‘H’).
In the above-mentioned conventional EPROM, the program mode signal ˜PGM inputted to the data write circuits 401 and 402 is at H-level, the outputs of the NOR gates 42 and 43 are at L-level, and then the NMOS transistors 44 and 45 are both OFF. As a result, the output (namely, the node N40) of the data write circuits 401 and 402 is in a high impedance state. At this time, a current path from the memory cells 11a, 11b, 11c and 11d to the ground voltage GND does not exist, so if the memory cells 11a, 11b, 11c and 11d are in the logical value ‘H’ state, as shown in FIG. 18, the drain lines DL0, DL1 and DL2, the source lines SL0 and SL1, and the bit lines BL0 and BL1 go up to the drain drive voltage MCD, i.e., VCC+2Vtn, (=6 V) via the memory cells 11a, 11b, 11c and 11d, respectively.
Here, if the logical value ‘L’ is written into the memory cell 11a and the logical value ‘H’ is written into the memory cell 11d, the program mode signal ˜PGM inputted to the data write circuits 401 and 402 is at L-level, the write signal BLA1 outputted from the data write circuit 40, is at L-level, and the write signal BLA2 outputted from the data write circuit 402 is at H-level. Then, as shown in FIG. 19, the bit line BL0 and source SOUab are at ground voltage GND (=0 V), and the bit line BL1 and source SOUcd are at a voltage VCC−Vtn (=3 V). At this time, as shown by the arrow Ia2, current flows from the drain DRa to the source SOUab at GND voltage, electrons are injected into the floating gate FGa by an avalanche hot carrier, and the logical value ‘L’ is written into the memory cell 11a. Also, only a small current Id2 flows from the drain DRd to the source SOUcd at the voltage VCC−Vtn, so electrons are not injected into the floating gate FGd by an avalanche hot carrier, and the logical value ‘H’ is written into the memory cell 11d. 
However, before data write to the memory cells 11a and 11d shown in FIG. 19 (at a time shown in FIG. 18), when data write occurs, the charge (voltage VCC+2Vtn) stored in the bit line BL1 and drain line DL1 is discharged through the source line SL0 and bit line BL0 at GND level, e.g., via the memory cell 11b. Due to this discharge current (e.g., current Ib in FIG. 19), electrons may be injected into the floating gate FGb of the memory cell 11b, and incorrect write of data to the memory cell 11b which is not selected, may arise. Moreover, if the threshold voltage Vt of the memory cell increases due to injection of electrons into the floating gate, an access delay may occur and the operating power supply voltage may change.